Signal Processing Engineer
At EVONA we are looking for an experienced SDR signal processing engineer to assist in the full life-cycle development of our client's satellite payloads.
You will directly participate in the architecture definition, development, testing and deployment of the DSP modules on the satellite payloads. You will interface directly with the satellite design team, payload design team, partners and other software developers to build up and continuously improve payload applications.
Location: This position will be preferable based in Barcelona (HQ), but fully remote option will be considered as well as other office locations such as Madrid, Vigo and Bilbao.
Responsibilities of the role:
- Work together with the Space Infrastructure team and the Payload team to define signal processing requirements for our applications
- Support transition of signal processing algorithms from scientific development tools to real time software environments such as C/C++ or Python using agile methodology
- Ensure that signal processing application is thoroughly tested and coordinated throughout the development life cycle, with an emphasis on satellite operations and client expectations.
- Design of testing procedures and automated routines
- Final signal processing application testing and validation on SDR platforms on the flight satellite.
- Active collaboration in other software projects of the company.
- BsC or MsC in Telecommunications, Engineering and/or Physics specialized in Signal Processing.
- Open minded software developer with 3 -5 years’ experience in Signal Processing, Communications Signals, Signal Intelligence (SIGINT), and/or Software-Defined Radios (SDR)
- Designing, analysing, modelling and simulating signal processing algorithms such as multi-frequency communications, signals collection or RF geolocation.
- Experience with SDR frameworks such as GNU Radio, GRC, SCA, REDHAWK, and/or OpenCPI
- Experience with signal processing techniques (energy detection, channelization, phase coherency, doppler compensation, demodulation, etc)
- Experience in Xilinx FPGA Hardware environments for design/debug on VHDL and interfacing with SRAM, DDR3&4 DRAM, Flash or High-Speed Serial I/O.
- Experience in high-speed signal integrity issues.